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Searched refs:DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_sh_mask.h3903 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_sh_mask.h37282 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT … macro
H A Dnbio_6_1_sh_mask.h22573 #define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT … macro