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Searched refs:DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h20734 #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 macro
H A Dgfx_8_1_sh_mask.h21346 #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h29698 #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT … macro
H A Dgc_9_1_sh_mask.h31025 #define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT … macro