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Searched refs:DIDT_SQ_CTRL0__PHASE_OFFSET_MASK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_powertune.c144 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
286 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
428 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
571 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
754 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ…
H A Dvega10_powertune.c211 …{ ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFF…
/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h18271 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_0_sh_mask.h20489 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
H A Dgfx_8_1_sh_mask.h21091 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28596 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK macro
H A Dgc_9_1_sh_mask.h29942 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK macro
H A Dgc_9_2_1_sh_mask.h30265 #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK macro