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Searched refs:DISP1_GAP_MCHG_MASK (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drv6xxd.h140 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
H A Drv770d.h265 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
H A Dsid.h311 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
H A Drv770_dpm.c886 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in rv770_enable_display_gap()
1350 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in rv770_program_display_gap()
H A Devergreend.h203 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
H A Dcypress_dpm.c1736 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in cypress_enable_display_gap()
H A Drv6xx_dpm.c1185 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in rv6xx_program_display_gap()
H A Dsi_dpm.c3805 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in si_enable_display_gap()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c4271 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in si_enable_display_gap()