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Searched refs:DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_sh_mask.h8441 #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 macro
H A Ddce_11_0_sh_mask.h8115 #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 macro
H A Ddce_11_2_sh_mask.h9371 #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK 0x2000000 macro
H A Ddce_12_0_sh_mask.h5432 #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h4530 #define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK … macro