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Searched refs:DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_sh_mask.h8111 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 macro
H A Ddce_11_0_sh_mask.h8001 #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 macro