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Searched refs:DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c45 #ifndef DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK
46 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK 0x00000400L macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h3596 #define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK macro