Home
last modified time | relevance | path

Searched refs:DPLL_CTRL1_LINK_RATE (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_cdclk.c775 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): in skl_dpll0_update()
776 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): in skl_dpll0_update()
777 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): in skl_dpll0_update()
778 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): in skl_dpll0_update()
781 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): in skl_dpll0_update()
782 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): in skl_dpll0_update()
882 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, in skl_dpll0_enable()
885 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, in skl_dpll0_enable()
H A Dintel_dpll_mgr.c1337 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); in skl_ddi_dp_set_dpll_hw_state()
1340 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); in skl_ddi_dp_set_dpll_hw_state()
1343 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); in skl_ddi_dp_set_dpll_hw_state()
1347 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0); in skl_ddi_dp_set_dpll_hw_state()
1350 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0); in skl_ddi_dp_set_dpll_hw_state()
1353 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0); in skl_ddi_dp_set_dpll_hw_state()
H A Di915_reg.h8544 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1)) macro