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Searched refs:DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_2_sh_mask.h1560 #define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 macro
H A Dsmu_7_1_3_sh_mask.h1978 #define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 macro