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Searched refs:DPM_TABLE_42__VddGfxLevelCount_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_2_sh_mask.h1067 #define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff macro
H A Dsmu_7_1_3_sh_mask.h1479 #define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff macro