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Searched refs:G4X_WM_LEVEL_SR (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_pm.c1045 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; in g4x_setup_wm_latency()
1083 case G4X_WM_LEVEL_SR: in g4x_fbc_fifo_size()
1180 level = max(level, G4X_WM_LEVEL_SR); in g4x_raw_fbc_wm_set()
1260 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, in g4x_raw_plane_wm_compute()
1299 if (level <= G4X_WM_LEVEL_SR) { in g4x_invalidate_wms()
1352 level = G4X_WM_LEVEL_SR; in g4x_compute_pipe_wm()
1393 if (level >= G4X_WM_LEVEL_SR && in g4x_compute_pipe_wm()
1394 wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) in g4x_compute_pipe_wm()
1442 g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) || in g4x_compute_intermediate_wm()
1444 g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) && in g4x_compute_intermediate_wm()
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H A Dintel_drv.h539 G4X_WM_LEVEL_SR, enumerator