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Searched refs:GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_1_sh_mask.h8652 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT macro
H A Dgc_9_2_1_sh_mask.h8491 #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT macro