Home
last modified time | relevance | path

Searched refs:GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h4310 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L macro
H A Dgfx_7_2_sh_mask.h14613 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 macro
H A Dgfx_8_0_sh_mask.h16541 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 macro
H A Dgfx_8_1_sh_mask.h17129 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h4625 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK … macro
H A Dgc_9_1_sh_mask.h4198 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK … macro
H A Dgc_9_2_1_sh_mask.h4104 #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK … macro