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Searched refs:GEN6_VEVSYNC (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_ringbuffer.c1963 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, in intel_ring_init_semaphores()
H A Di915_reg.h2302 #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) macro