Searched refs:HAL_TXDESC_RTSENA (Results 1 – 8 of 8) sorted by relevance
268 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) in ath_tx_rate_fill_rcflags()809 (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { in ath_tx_form_aggr()834 ~ (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); in ath_tx_form_aggr()837 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); in ath_tx_form_aggr()
1079 flags |= HAL_TXDESC_RTSENA; in ath_tx_calc_protection()1104 flags |= HAL_TXDESC_RTSENA; in ath_tx_calc_protection()1224 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ in ath_tx_calc_ctsduration()1231 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ in ath_tx_calc_ctsduration()1268 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { in ath_tx_set_rtscts()1756 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ in ath_tx_normal_setup()2173 flags |= HAL_TXDESC_RTSENA; in ath_tx_raw_start()2212 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) in ath_tx_raw_start()
337 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) in ar5416SetupTxDesc()405 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0) in ar5416SetupTxDesc()618 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) in ar5416SetupFirstTxDesc()654 | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0); in ar5416SetupFirstTxDesc()883 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { in ar5416Set11nRateScenario()886 if (flags & HAL_TXDESC_RTSENA) { in ar5416Set11nRateScenario()
273 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ macro
718 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { in ar9300_set_11n_rate_scenario()719 if (flags & HAL_TXDESC_RTSENA) { in ar9300_set_11n_rate_scenario()
704 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) in ar5212SetupTxDesc()751 | (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0) in ar5212SetupTxDesc()
519 if (flags & HAL_TXDESC_RTSENA) { in ar5210SetupTxDesc()
541 | (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0) in ar5211SetupTxDesc()