Searched refs:HBB_RWBUFFER (Results 1 – 2 of 2) sorted by relevance
/dragonfly/sys/dev/raid/arcmsr/ |
H A D | arcmsr.c | 1711 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); in arcmsr_dr_handle() 1809 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); in arcmsr_hbb_message_isr() 3692 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); in arcmsr_get_hbb_config() 3720 …acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_le… in arcmsr_get_hbb_config() 3722 …acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size… in arcmsr_get_hbb_config() 3723 …acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channe… in arcmsr_get_hbb_config() 4086 …CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero… in arcmsr_iop_confirm() 4087 …CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*… in arcmsr_iop_confirm() 4088 …CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (25… in arcmsr_iop_confirm() 4089 …CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8… in arcmsr_iop_confirm() [all …]
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H A D | arcmsr.h | 536 struct HBB_RWBUFFER struct 556 struct HBB_RWBUFFER *hbb_rwbuffer; argument
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