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Searched refs:HDMI0_ACR_48_0 (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Ddce3_1_afmt.c204 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr()
H A Dr600_hdmi.c208 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr()
H A Dr600d.h1154 #define HDMI0_ACR_48_0 0x74bc macro