/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | vega10_ih.c | 49 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in vega10_ih_enable_interrupts() 50 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in vega10_ih_enable_interrupts() 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in vega10_ih_disable_interrupts() 67 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in vega10_ih_disable_interrupts() 105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 1); in vega10_ih_irq_init() 109 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SPACE, 4); in vega10_ih_irq_init() 117 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); in vega10_ih_irq_init() 118 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); in vega10_ih_irq_init() 119 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in vega10_ih_irq_init() 122 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); in vega10_ih_irq_init() [all …]
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H A D | tonga_ih.c | 62 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts() 63 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts() 79 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts() 80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts() 127 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init() 128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init() 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in tonga_ih_irq_init() 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in tonga_ih_irq_init() 134 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); in tonga_ih_irq_init() 215 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_get_wptr()
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H A D | cz_ih.c | 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts() 82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts() 128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init() 129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init() 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init() 133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in cz_ih_irq_init() 204 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_get_wptr()
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H A D | iceland_ih.c | 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts() 82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts() 128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init() 129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init() 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init() 133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in iceland_ih_irq_init() 204 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_get_wptr()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | r600.c | 3607 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts() 3612 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts() 3618 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts() 3623 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts() 3735 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init() 4069 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr() 4071 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
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H A D | si.c | 5909 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts() 5914 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts() 5920 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts() 5925 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts() 6011 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init() 6214 tmp = RREG32(IH_RB_CNTL); in si_get_ih_wptr() 6216 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
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H A D | cik.c | 6863 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts() 6868 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts() 6881 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts() 6886 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts() 7030 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init() 7478 tmp = RREG32(IH_RB_CNTL); in cik_get_ih_wptr() 7480 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
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H A D | sid.h | 651 #define IH_RB_CNTL 0x3e00 macro
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H A D | cikd.h | 801 #define IH_RB_CNTL 0x3e00 macro
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H A D | evergreend.h | 1220 #define IH_RB_CNTL 0x3e00 macro
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H A D | r600d.h | 659 #define IH_RB_CNTL 0x3e00 macro
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H A D | evergreen.c | 4675 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr() 4677 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()
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