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Searched refs:MAX_MPCC (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.h49 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
50 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
51 uint32_t MPCC_CONTROL[MAX_MPCC]; \
52 uint32_t MPCC_STATUS[MAX_MPCC]; \
53 uint32_t MPCC_OPP_ID[MAX_MPCC]; \
54 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
55 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
56 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
57 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
H A Ddcn10_mpc.c463 for (i = 0; i < MAX_MPCC; i++) in dcn10_mpc_construct()
/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
H A Dmpc.h31 #define MAX_MPCC 6 macro
105 struct mpcc mpcc_array[MAX_MPCC];