Searched refs:MI_SEMAPHORE_SYNC_RVE (Results 1 – 2 of 2) sorted by relevance
1958 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, in intel_ring_init_semaphores()
512 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ macro