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Searched refs:MP0_BASE (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvega20_reg_init.c40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
H A Dvega10_reg_init.c40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
/dragonfly/sys/dev/drm/amd/include/
H A Dvega20_ip_offset.h87 static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, variable
H A Dvega10_ip_offset.h58 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } }, variable