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Searched refs:MP0_BASE__INST0_SEG1 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/
H A Dvega20_ip_offset.h505 #define MP0_BASE__INST0_SEG1 0 macro
H A Dvega10_ip_offset.h336 #define MP0_BASE__INST0_SEG1 0 macro