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Searched refs:MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/mp/
H A Dmp_10_0_sh_mask.h255 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK macro
H A Dmp_9_0_sh_mask.h260 #define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L macro