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Searched refs:MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h11326 #define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x00020000L macro
H A Dgmc_7_1_sh_mask.h9563 #define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000 macro
H A Dgmc_8_1_sh_mask.h10477 #define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000 macro