Searched refs:MPLL_FUNC_CNTL_1 (Results 1 – 8 of 8) sorted by relevance
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/ |
H A D | iceland_smumgr.c | 1077 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); in iceland_calculate_mclk_params() 1079 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); in iceland_calculate_mclk_params() 1081 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); in iceland_calculate_mclk_params()
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H A D | ci_smumgr.c | 1051 MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf); in ci_calculate_mclk_params() 1053 MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac); in ci_calculate_mclk_params() 1055 MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode); in ci_calculate_mclk_params()
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H A D | tonga_smumgr.c | 813 MPLL_FUNC_CNTL_1, CLKF, in tonga_calculate_mclk_params() 816 MPLL_FUNC_CNTL_1, CLKFRAC, in tonga_calculate_mclk_params() 819 MPLL_FUNC_CNTL_1, VCO_MODE, in tonga_calculate_mclk_params()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | sid.h | 615 #define MPLL_FUNC_CNTL_1 0x2bb8 macro
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H A D | cikd.h | 738 #define MPLL_FUNC_CNTL_1 0x2bb8 macro
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H A D | ci_dpm.c | 1925 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
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H A D | si_dpm.c | 3581 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in si_read_clock_registers()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | si_dpm.c | 4041 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in si_read_clock_registers()
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