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Searched refs:PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5576 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000c000L macro
H A Dgfx_7_2_sh_mask.h5579 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 macro
H A Dgfx_8_0_sh_mask.h6367 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 macro
H A Dgfx_8_1_sh_mask.h6901 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16790 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK … macro
H A Dgc_9_1_sh_mask.h18224 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK … macro
H A Dgc_9_2_1_sh_mask.h18100 #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK … macro