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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h5589 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x00000003 macro
H A Dgfx_7_2_sh_mask.h5572 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 macro
H A Dgfx_8_0_sh_mask.h6360 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 macro
H A Dgfx_8_1_sh_mask.h6894 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16767 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT … macro
H A Dgc_9_1_sh_mask.h18201 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h18076 #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT … macro