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Searched refs:PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h6891 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0x0000000a macro
H A Dgfx_7_2_sh_mask.h5800 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa macro
H A Dgfx_8_0_sh_mask.h6588 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa macro
H A Dgfx_8_1_sh_mask.h7122 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h21370 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … macro
H A Dgc_9_1_sh_mask.h22806 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h22757 #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT … macro