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Searched refs:PCH_DPLL_SEL (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_display.c4508 temp = I915_READ(PCH_DPLL_SEL); in ironlake_pch_enable()
4516 I915_WRITE(PCH_DPLL_SEL, temp); in ironlake_pch_enable()
5525 temp = I915_READ(PCH_DPLL_SEL); in ironlake_crtc_disable()
5527 I915_WRITE(PCH_DPLL_SEL, temp); in ironlake_crtc_disable()
8649 tmp = I915_READ(PCH_DPLL_SEL); in ironlake_get_pipe_config()
H A Di915_reg.h7306 #define PCH_DPLL_SEL _MMIO(0xc7000) macro