Searched refs:PCIE_CNTL2 (Results 1 – 5 of 5) sorted by relevance
| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | gmc_v7_0.c | 857 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); in gmc_v7_0_enable_bif_mgls()
858 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); in gmc_v7_0_enable_bif_mgls()
859 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); in gmc_v7_0_enable_bif_mgls()
860 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); in gmc_v7_0_enable_bif_mgls()
862 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); in gmc_v7_0_enable_bif_mgls()
863 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); in gmc_v7_0_enable_bif_mgls()
864 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); in gmc_v7_0_enable_bif_mgls()
865 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); in gmc_v7_0_enable_bif_mgls()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | sid.h | 1473 #define PCIE_CNTL2 0x1c /* PCIE */ macro
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| H A D | cikd.h | 330 #define PCIE_CNTL2 0x1001001c /* PCIE */ macro
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| H A D | si.c | 5558 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()
5568 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls()
7435 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
7438 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
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| H A D | cik.c | 6279 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2); in cik_enable_bif_mgls()
6289 WREG32_PCIE_PORT(PCIE_CNTL2, data); in cik_enable_bif_mgls()
9766 orig = data = RREG32_PCIE_PORT(PCIE_CNTL2); in cik_program_aspm()
9769 WREG32_PCIE_PORT(PCIE_CNTL2, data); in cik_program_aspm()
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