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Searched refs:PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_sh_mask.h586 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h1618 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc macro
H A Dbif_5_0_sh_mask.h1854 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc macro
H A Dbif_5_1_sh_mask.h1722 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_sh_mask.h3985 #define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT … macro