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Searched refs:PIPE0_DMIF_BUFFER_CONTROL (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_mem_input.h183 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
184 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
/dragonfly/sys/dev/drm/radeon/
H A Dsid.h328 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
H A Dcikd.h440 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
H A Devergreend.h1216 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 macro
H A Devergreen.c1852 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
1855 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
H A Dsi.c1993 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
1996 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
H A Dcik.c8823 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
8826 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c619 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v10_0_line_buffer_adjust()
624 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v10_0_line_buffer_adjust()
H A Ddce_v11_0.c645 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); in dce_v11_0_line_buffer_adjust()
650 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) in dce_v11_0_line_buffer_adjust()