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Searched refs:PIPE0_LATENCY_CONTROL (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Devergreend.h1212 #define PIPE0_LATENCY_CONTROL 0x0bf4 macro
H A Devergreen.c2271 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2279 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()