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Searched refs:PIPECONF_BPC_MASK (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_display.c1715 val &= ~PIPECONF_BPC_MASK; in ironlake_enable_pch_transcoder()
1719 val |= pipeconf_val & PIPECONF_BPC_MASK; in ironlake_enable_pch_transcoder()
4128 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
4200 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4228 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
4539 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
7510 switch (tmp & PIPECONF_BPC_MASK) { in i9xx_get_pipe_config()
8610 switch (tmp & PIPECONF_BPC_MASK) { in ironlake_get_pipe_config()
H A Di915_reg.h5355 #define PIPECONF_BPC_MASK (0x7 << 5) macro