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Searched refs:PIPESRC (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_display.c3702 I915_WRITE(PIPESRC(crtc->pipe), in intel_update_pipe_config()
7009 I915_WRITE(PIPESRC(pipe), in intel_set_pipe_src_size()
7056 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_src_size()
7434 val = I915_READ(PIPESRC(pipe)); in i9xx_get_initial_plane_config()
8570 val = I915_READ(PIPESRC(pipe)); in ironlake_get_initial_plane_config()
14650 I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); in i830_enable_pipe()
15426 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
H A Di915_reg.h3951 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) macro