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Searched refs:PIPE_CONTROL_QW_WRITE (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_ringbuffer.c198 *cs++ = PIPE_CONTROL_QW_WRITE; in intel_emit_post_sync_nonzero_flush()
244 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; in gen6_render_ring_flush()
316 flags |= PIPE_CONTROL_QW_WRITE; in gen7_render_ring_flush()
365 flags |= PIPE_CONTROL_QW_WRITE; in gen8_render_ring_flush()
728 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_QW_WRITE | in gen8_rcs_signal()
857 PIPE_CONTROL_QW_WRITE; in gen8_render_emit_breadcrumb()
H A Dintel_lrc.c1266 PIPE_CONTROL_QW_WRITE, in gen8_init_indirectctx_bb()
1306 PIPE_CONTROL_QW_WRITE, in gen9_init_indirectctx_bb()
1750 flags |= PIPE_CONTROL_QW_WRITE; in gen8_emit_flush_render()
1837 PIPE_CONTROL_QW_WRITE; in gen8_emit_breadcrumb_render()
H A Di915_reg.h632 #define PIPE_CONTROL_QW_WRITE (1<<14) macro