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Searched refs:PIXCLK_RESYNC_CNTL (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_clock_source.h42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
61 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
104 uint32_t PIXCLK_RESYNC_CNTL; member
H A Ddce_clock_source.c895 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, in dce112_program_pixel_clk_resync()
899 REG_UPDATE(PIXCLK_RESYNC_CNTL, in dce112_program_pixel_clk_resync()