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Searched refs:PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_sh_mask.h18365 #define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT 0x10 macro
H A Ddce_12_0_sh_mask.h360 #define PPLL_FREQ_CTRL0__reg_tmg_fcw0_int__SHIFT macro