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Searched refs:PPSMC_MSG_SetHardMinFclkByFreq (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu10_hwmgr.c77 msg = PPSMC_MSG_SetHardMinFclkByFreq; in smu10_display_clock_voltage_request()
561 PPSMC_MSG_SetHardMinFclkByFreq, in smu10_dpm_force_dpm_level()
593 PPSMC_MSG_SetHardMinFclkByFreq, in smu10_dpm_force_dpm_level()
604 PPSMC_MSG_SetHardMinFclkByFreq, in smu10_dpm_force_dpm_level()
631 PPSMC_MSG_SetHardMinFclkByFreq, in smu10_dpm_force_dpm_level()
664 PPSMC_MSG_SetHardMinFclkByFreq, in smu10_dpm_force_dpm_level()
834 PPSMC_MSG_SetHardMinFclkByFreq, in smu10_force_clock_level()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Drv_ppsmc.h50 #define PPSMC_MSG_SetHardMinFclkByFreq 0x12 macro