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Searched refs:PP_STATE_LS (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_clockpowergating.c188 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS in smu7_update_clock_gatings()
212 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
225 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
238 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
282 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
306 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
329 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
353 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
377 msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS ? in smu7_update_clock_gatings()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvi.c1369 pp_state = PP_STATE_LS; in vi_common_set_clockgating_state_by_smu()
1388 pp_state = PP_STATE_LS; in vi_common_set_clockgating_state_by_smu()
1407 pp_state = PP_STATE_LS; in vi_common_set_clockgating_state_by_smu()
1428 pp_state = PP_STATE_LS; in vi_common_set_clockgating_state_by_smu()
1456 pp_state = PP_STATE_LS; in vi_common_set_clockgating_state_by_smu()
H A Dgfx_v8_0.c6109 pp_state = PP_STATE_LS; in gfx_v8_0_tonga_update_gfx_clock_gating()
6129 pp_state = PP_STATE_LS; in gfx_v8_0_tonga_update_gfx_clock_gating()
6161 pp_state = PP_STATE_LS; in gfx_v8_0_polaris_update_gfx_clock_gating()
6181 pp_state = PP_STATE_LS; in gfx_v8_0_polaris_update_gfx_clock_gating()
6201 pp_state = PP_STATE_LS; in gfx_v8_0_polaris_update_gfx_clock_gating()
6226 pp_state = PP_STATE_LS; in gfx_v8_0_polaris_update_gfx_clock_gating()
6242 pp_state = PP_STATE_LS; in gfx_v8_0_polaris_update_gfx_clock_gating()
/dragonfly/sys/dev/drm/amd/include/
H A Dkgd_pp_interface.h177 #define PP_STATE_LS 0x02 macro