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Searched refs:RADEON_CLOCK_CNTL_INDEX (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dradeon_legacy_crtc.c940 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
961 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
H A Dr100.c2882 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2884 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); in r100_pll_errata_after_data()
2886 WREG32(RADEON_CLOCK_CNTL_INDEX, save); in r100_pll_errata_after_data()
2896 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
2909 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
H A Dradeon_legacy_tv.c286 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
H A Dradeon_legacy_encoders.c236 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); in radeon_legacy_lvds_mode_set()
H A Dradeon_reg.h346 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
H A Dradeon_combios.c1142 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()