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Searched refs:RADEON_CP_RB_CNTL (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drs600.c466 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset()
467 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in rs600_asic_reset()
470 WREG32(RADEON_CP_RB_CNTL, tmp); in rs600_asic_reset()
H A Dr300.c421 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset()
422 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r300_asic_reset()
425 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()
H A Dr100.c1185 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); in r100_cp_init()
1191 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); in r100_cp_init()
1208 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_cp_init()
2581 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2582 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r100_asic_reset()
2585 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_asic_reset()
4030 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4032 WREG32(RADEON_CP_RB_CNTL, 0); in r100_restore_sanity()
H A Dradeon_reg.h3297 #define RADEON_CP_RB_CNTL 0x0704 macro