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Searched refs:RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7129 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000 macro
H A Dgfx_7_2_sh_mask.h7834 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h8736 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h9288 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h22916 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_9_1_sh_mask.h24332 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h24383 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro