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Searched refs:RREG32 (Results 1 – 25 of 105) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
H A Dradeon_bios.c287 bus_cntl = RREG32(R600_BUS_CNTL);
291 rom_cntl = RREG32(R600_ROM_CNTL);
336 bus_cntl = RREG32(R600_BUS_CNTL);
340 rom_cntl = RREG32(R600_ROM_CNTL);
411 bus_cntl = RREG32(R600_BUS_CNTL);
415 rom_cntl = RREG32(R600_ROM_CNTL);
488 bus_cntl = RREG32(RV370_BUS_CNTL);
492 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
493 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
550 bus_cntl = RREG32(RV370_BUS_CNTL);
[all …]
H A Dradeon_legacy_encoders.c662 dac_cntl = RREG32(RADEON_DAC_CNTL); in radeon_legacy_primary_dac_detect()
1226 dac_cntl = RREG32(RADEON_DAC_CNTL); in radeon_legacy_tv_dac_mode_set()
1315 gpiopad_a = RREG32(RADEON_GPIOPAD_A); in r300_legacy_tv_detect()
1316 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); in r300_legacy_tv_detect()
1344 RREG32(RADEON_TV_DAC_CNTL); in r300_legacy_tv_detect()
1355 RREG32(RADEON_TV_DAC_CNTL); in r300_legacy_tv_detect()
1358 tmp = RREG32(RADEON_TV_DAC_CNTL); in r300_legacy_tv_detect()
1388 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); in radeon_legacy_tv_detect()
1424 tmp = RREG32(RADEON_TV_DAC_CNTL); in radeon_legacy_tv_detect()
1469 tmp = RREG32(RADEON_GPIO_MONID); in radeon_legacy_ext_dac_detect()
[all …]
H A Dradeon_i2c.c187 val = RREG32(rec->y_clk_reg); in get_clock()
202 val = RREG32(rec->y_data_reg); in get_data()
479 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
482 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
511 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
514 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
539 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
542 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
609 tmp = RREG32(rec->a_clk_reg); in r500_hw_i2c_xfer()
612 tmp = RREG32(rec->a_clk_reg); in r500_hw_i2c_xfer()
[all …]
H A Drs600.c226 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
235 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
466 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset()
478 RREG32(R_0000F0_RBBM_SOFT_RESET); in rs600_asic_reset()
486 RREG32(R_0000F0_RBBM_SOFT_RESET); in rs600_asic_reset()
494 RREG32(R_0000F0_RBBM_SOFT_RESET); in rs600_asic_reset()
702 RREG32(R_000040_GEN_INT_CNTL); in rs600_irq_set()
1044 RREG32(R_000E40_RBBM_STATUS), in rs600_resume()
1045 RREG32(R_0007C0_CP_STAT)); in rs600_resume()
1119 RREG32(R_000E40_RBBM_STATUS), in rs600_init()
[all …]
H A Dvce_v2_0.c43 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
47 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
51 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
57 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
62 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
67 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
77 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
87 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
134 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
140 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
[all …]
H A Dvce_v1_0.c63 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
65 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
80 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
82 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
108 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
112 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
121 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
140 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_init_cg()
144 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v1_0_init_cg()
149 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_init_cg()
[all …]
H A Dr600.c117 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
173 *val = RREG32(reg); in r600_get_allowed_info_register()
1433 tmp = RREG32(RAMCFG); in r600_mc_init()
1441 tmp = RREG32(CHMAP); in r600_mc_init()
1572 RREG32(CP_STAT)); in r600_print_gpu_status_regs()
1848 tmp = RREG32(BUS_CNTL); in r600_gpu_pci_config_reset()
2371 tmp = RREG32(ARB_POP); in r600_gpu_init()
2856 tmp = RREG32(scratch); in r600_ring_test()
3450 tmp = RREG32(scratch); in r600_ib_test()
4121 RREG32(IH_RB_WPTR); in r600_irq_process()
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H A Drv730_dpm.c203 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
205 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
207 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
209 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
211 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
214 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
216 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
218 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
220 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
222 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
H A Dr100.c735 RREG32(RADEON_GEN_INT_CNTL); in r100_irq_set()
2560 tmp = RREG32(RADEON_BUS_CNTL); in r100_bm_disable()
2797 tom = RREG32(RADEON_NB_TOM); in r100_vram_init_sizes()
3043 tmp = RREG32(RADEON_BUS_CNTL); in r100_debugfs_mc_info()
3047 tmp = RREG32(RADEON_AGP_BASE); in r100_debugfs_mc_info()
3051 tmp = RREG32(0x01D0); in r100_debugfs_mc_info()
3057 tmp = RREG32(0x01E4); in r100_debugfs_mc_info()
3684 tmp = RREG32(scratch); in r100_ring_test()
3761 tmp = RREG32(scratch); in r100_ib_test()
3968 RREG32(R_0007C0_CP_STAT)); in r100_resume()
[all …]
H A Drs400.c242 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
257 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
284 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
307 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info()
309 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info()
325 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info()
327 tmp = RREG32(RS480_AGP_BASE_2); in rs400_debugfs_gart_info()
467 RREG32(R_000E40_RBBM_STATUS), in rs400_resume()
468 RREG32(R_0007C0_CP_STAT)); in rs400_resume()
541 RREG32(R_000E40_RBBM_STATUS), in rs400_init()
[all …]
H A Dcik.c160 *val = RREG32(reg); in cik_get_allowed_info_register()
239 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
240 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
251 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
253 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
3510 tmp = RREG32(scratch); in cik_ring_test()
3855 tmp = RREG32(scratch); in cik_ib_test()
4831 RREG32(GRBM_STATUS)); in cik_print_gpu_status_regs()
4833 RREG32(GRBM_STATUS2)); in cik_print_gpu_status_regs()
4843 RREG32(SRBM_STATUS)); in cik_print_gpu_status_regs()
[all …]
H A Devergreen.c1089 *val = RREG32(reg); in evergreen_get_allowed_info_register()
3059 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3062 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3753 RREG32(GRBM_STATUS)); in evergreen_print_gpu_status_regs()
3755 RREG32(GRBM_STATUS_SE0)); in evergreen_print_gpu_status_regs()
3759 RREG32(SRBM_STATUS)); in evergreen_print_gpu_status_regs()
3761 RREG32(SRBM_STATUS2)); in evergreen_print_gpu_status_regs()
3767 RREG32(CP_BUSY_STAT)); in evergreen_print_gpu_status_regs()
3769 RREG32(CP_STAT)); in evergreen_print_gpu_status_regs()
3771 RREG32(DMA_STATUS_REG)); in evergreen_print_gpu_status_regs()
[all …]
H A Dni.c47 r = RREG32(TN_SMC_IND_DATA_0); in tn_smc_rreg()
883 *val = RREG32(reg); in cayman_get_allowed_info_register()
1522 (void)RREG32(CP_RB0_WPTR); in cayman_gfx_set_wptr()
1680 RREG32(GRBM_SOFT_RESET); in cayman_cp_resume()
1683 RREG32(GRBM_SOFT_RESET); in cayman_cp_resume()
1761 tmp = RREG32(GRBM_STATUS); in cayman_gpu_check_soft_reset()
1796 tmp = RREG32(SRBM_STATUS); in cayman_gpu_check_soft_reset()
1846 RREG32(0x14F8)); in cayman_gpu_soft_reset()
1848 RREG32(0x14D8)); in cayman_gpu_soft_reset()
1850 RREG32(0x14FC)); in cayman_gpu_soft_reset()
[all …]
H A Dr420.c133 tmp = RREG32(R300_DST_PIPE_CONFIG); in r420_pipes_init()
137 RREG32(R300_RB2D_DSTCACHE_MODE) | in r420_pipes_init()
146 tmp = RREG32(RV530_GB_PIPE_SELECT2); in r420_pipes_init()
165 r = RREG32(R_0001FC_MC_IND_DATA); in r420_mc_rreg()
315 RREG32(R_000E40_RBBM_STATUS), in r420_resume()
316 RREG32(R_0007C0_CP_STAT)); in r420_resume()
406 RREG32(R_000E40_RBBM_STATUS), in r420_init()
407 RREG32(R_0007C0_CP_STAT)); in r420_init()
483 tmp = RREG32(R400_GB_PIPE_SELECT); in r420_debugfs_pipes_info()
485 tmp = RREG32(R300_GB_TILE_CONFIG); in r420_debugfs_pipes_info()
[all …]
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgmc_v8_0.c393 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
776 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v8_0_set_prt()
850 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_enable()
859 tmp = RREG32(mmVM_L2_CNTL2); in gmc_v8_0_gart_enable()
865 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v8_0_gart_enable()
871 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
986 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_disable()
1557 data = RREG32(mmVM_L2_CG); in fiji_update_mc_medium_grain_clock_gating()
1593 data = RREG32(mmVM_L2_CG); in fiji_update_mc_medium_grain_clock_gating()
1637 data = RREG32(mmVM_L2_CG); in fiji_update_mc_light_sleep()
[all …]
H A Dgmc_v7_0.c276 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
301 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
328 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v7_0_mc_init()
334 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v7_0_mc_init()
518 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_set_fault_enable_default()
549 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v7_0_set_prt()
623 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_enable()
637 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v7_0_gart_enable()
691 tmp = RREG32(mmCHUB_CONTROL); in gmc_v7_0_gart_enable()
742 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_disable()
[all …]
H A Damdgpu_i2c.c50 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
56 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
59 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
63 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
72 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
76 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
91 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_post_xfer()
95 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_post_xfer()
108 val = RREG32(rec->y_clk_reg); in amdgpu_i2c_get_clock()
123 val = RREG32(rec->y_data_reg); in amdgpu_i2c_get_data()
[all …]
H A Dcz_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
147 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
203 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
358 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
374 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
386 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_soft_reset()
393 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
397 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
[all …]
H A Diceland_ih.c60 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
80 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
147 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
203 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
358 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
374 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
386 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_soft_reset()
393 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
397 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
[all …]
H A Dvce_v3_0.c91 v = RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
93 v = RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
95 v = RREG32(mmVCE_RB_RPTR3); in vce_v3_0_ring_get_rptr()
123 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
125 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
127 v = RREG32(mmVCE_RB_WPTR3); in vce_v3_0_ring_get_wptr()
183 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
209 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
663 tmp = RREG32(mmSRBM_SOFT_RESET); in vce_v3_0_soft_reset()
667 tmp = RREG32(mmSRBM_SOFT_RESET); in vce_v3_0_soft_reset()
[all …]
H A Dvce_v4_0.c66 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr()
68 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2)); in vce_v4_0_ring_get_rptr()
70 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3)); in vce_v4_0_ring_get_rptr()
88 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR)); in vce_v4_0_ring_get_wptr()
90 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2)); in vce_v4_0_ring_get_wptr()
92 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3)); in vce_v4_0_ring_get_wptr()
131 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded()
669 return !(RREG32(mmSRBM_STATUS2) & mask);
743 tmp = RREG32(mmSRBM_SOFT_RESET);
747 tmp = RREG32(mmSRBM_SOFT_RESET);
[all …]
H A Damdgpu_amdkfd_gfx_v8.c336 value = RREG32(mmRLC_CP_SCHEDULERS); in kgd_hqd_load()
398 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
447 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
452 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); in kgd_hqd_sdma_load()
531 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
536 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
537 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
604 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
652 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
864 RREG32(mmVM_INVALIDATE_RESPONSE); in invalidate_tlbs()
[all …]
H A Duvd_v5_0.c59 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_ring_get_rptr()
73 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v5_0_ring_get_wptr()
215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
366 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
512 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
615 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
616 data3 = RREG32(mmUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
661 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
662 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
709 data = RREG32(mmUVD_CGC_GATE);
[all …]
H A Ddce_v10_0.c406 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
435 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v10_0_set_vga_render_state()
443 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_set_vga_render_state()
481 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce()
656 u32 tmp = RREG32(mmMC_SHARED_CHMAP); in cik_get_number_of_dram_channels()
1531 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); in dce_v10_0_audio_set_dto()
1581 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1658 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
2915 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
2919 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
[all …]
H A Ddce_v11_0.c422 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
451 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v11_0_set_vga_render_state()
459 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_set_vga_render_state()
507 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce()
682 u32 tmp = RREG32(mmMC_SHARED_CHMAP); in cik_get_number_of_dram_channels()
1573 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); in dce_v11_0_audio_set_dto()
1623 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1700 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
3041 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3045 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
[all …]

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