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Searched refs:RREG32_NO_KIQ (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dmxgpu_vi.c324 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
329 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
338 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
346 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
357 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
373 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
378 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()
394 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
404 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
503 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq()
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H A Dmxgpu_ai.c55 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
65 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
137 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
179 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
226 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
278 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
H A Dgmc_v9_0.c345 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); in gmc_v9_0_flush_gpu_tlb()
356 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); in gmc_v9_0_flush_gpu_tlb()
H A Damdgpu_virt.c46 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
H A Dvega10_ih.c215 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); in vega10_ih_get_wptr()
H A Damdgpu_ttm.c1577 value = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_ttm_access_memory()
2258 value = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_ttm_vram_read()
H A Dvi.c116 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
H A Damdgpu.h1618 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro