Searched refs:RREG32_NO_KIQ (Results 1 – 8 of 8) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | mxgpu_vi.c | 324 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack() 329 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack() 338 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack() 346 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid() 357 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg() 373 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg() 378 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg() 394 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack() 404 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack() 503 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq() [all …]
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H A D | mxgpu_ai.c | 55 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg() 65 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg() 137 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg() 179 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests() 226 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq() 278 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
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H A D | gmc_v9_0.c | 345 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); in gmc_v9_0_flush_gpu_tlb() 356 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); in gmc_v9_0_flush_gpu_tlb()
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H A D | amdgpu_virt.c | 46 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
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H A D | vega10_ih.c | 215 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL)); in vega10_ih_get_wptr()
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H A D | amdgpu_ttm.c | 1577 value = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_ttm_access_memory() 2258 value = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_ttm_vram_read()
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H A D | vi.c | 116 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
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H A D | amdgpu.h | 1618 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro
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