Searched refs:RREG32_PCIE (Results 1 – 13 of 13) sorted by relevance
1439 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()1471 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1475 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1503 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()1561 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in cik_program_aspm()1566 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in cik_program_aspm()1571 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in cik_program_aspm()1682 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in cik_program_aspm()1690 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()1693 data = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_program_aspm()[all …]
152 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()180 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()201 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()206 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()267 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v6_1_init_registers()
153 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()191 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()212 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()217 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
65 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
1277 temp = data = RREG32_PCIE(ixPCIE_CNTL2); in vi_update_bif_medium_grain_light_sleep()1540 data = RREG32_PCIE(ixPCIE_CNTL2); in vi_common_get_clockgating_state()
242 value = RREG32_PCIE(*pos); in amdgpu_debugfs_regs_pcie_read()
854 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v7_0_enable_bif_mgls()
1631 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) macro
85 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()87 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()171 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()191 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()590 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info()592 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info()594 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); in rv370_debugfs_pcie_gart_info()596 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); in rv370_debugfs_pcie_gart_info()598 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); in rv370_debugfs_pcie_gart_info()600 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); in rv370_debugfs_pcie_gart_info()[all …]
5558 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()7151 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()7268 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()7435 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()7443 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
131 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv6xx_enable_pll_sleep_in_l1()
126 tmp = RREG32_PCIE(PCIE_P_CNTL); in rv770_enable_pll_sleep_in_l1()
2548 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) macro