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Searched refs:SCLK_FREQ_SETTING_STEP_0_PART1 (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dr600_dpm.c482 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_post_divider()
489 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_reference_divider()
496 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_feedback_divider()
503 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2), in r600_engine_clock_entry_set_step_time()
H A Dr600d.h1362 #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 macro