Searched refs:SCLK_FREQ_SETTING_STEP_0_PART2 (Results 1 – 2 of 2) sorted by relevance
450 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), in r600_engine_clock_entry_enable()453 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), in r600_engine_clock_entry_enable()461 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), in r600_engine_clock_entry_enable_pulse_skipping()464 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), in r600_engine_clock_entry_enable_pulse_skipping()472 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), in r600_engine_clock_entry_enable_post_divider()475 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2), in r600_engine_clock_entry_enable_post_divider()
1371 #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c macro