Searched refs:SDMA0_CNTL (Results 1 – 7 of 7) sorted by relevance
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | sdma_v3_0.c | 583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable() 585 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable() 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable() 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable() 1408 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state() 1413 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state() 1424 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state() 1429 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
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H A D | sdma_v2_4.c | 1072 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state() 1077 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state() 1088 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state() 1093 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
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H A D | sdma_v4_0.c | 569 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable() 696 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v4_0_gfx_resume() 1383 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | cik_reg.h | 206 #define SDMA0_CNTL 0xD010 macro
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H A D | cik_sdma.c | 312 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable() 317 WREG32(SDMA0_CNTL + reg_offset, value); in cik_sdma_ctx_switch_enable()
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H A D | cik.c | 6911 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state() 6912 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state() 6913 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state() 6914 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state() 7095 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set() 7096 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set() 7205 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set() 7206 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
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H A D | cikd.h | 1960 #define SDMA0_CNTL 0xD010 macro
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