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Searched refs:SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_sh_mask.h505 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1476 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
H A Doss_2_4_sh_mask.h1640 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
H A Doss_3_0_1_sh_mask.h2158 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro
H A Doss_3_0_sh_mask.h2462 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c macro